DDR4仿真深入探讨Ⅱ---DDR4链路与仿真细节分析（下）

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DDR4仿真深入探讨Ⅱ---DDR4链路与仿真细节分析（下）

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学习有效期 365 天（随到随学）

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课程介绍

感谢您使用电巢APP， PC端建议使用Google Chrome浏览器进行观看！

讲师介绍：

毛忠宇老师|EDA365信号完整性、仿真SI/PI论坛特邀版主，原国内知名企业高速信号仿真及SIP设计专家

20余年深耕电子科技行业，从事高速PCB设计、SI/PI仿真、PI仿真流程及仿真平台建设、高速IC封装设计等；
曾就职于深圳华为技术有限公司、海思半导体有限公司、兴森快捷电路科技股份有限公司，
EDA365论坛特邀版主。

主要出版物：

《芯片SiP封装与工程设计》
《信号、电源完整性仿真设计与高速产品应用实例》
《华为研发14载-那些一起奋斗过的互连岁月》
《IC封装基础与工程设计实例》

课程简介：

DDR4链路仿真中经常会涉及到一些看似简单但是又不好回答的问题，不同的问题站在不同角度看，回复的结果及建议会完全不一样。

如下面的一个普通问题：链路等长在芯片封装内绕好还是在PCB外绕好？

芯片封装设计的工程师会认为在PCB中绕合适，因为复杂的封装空间太小，不适合在里面绕线，而硬件工程师则认为在芯片封装内绕等长较好，这样对于用户来说更简单更方便，而PCB Layout工程师则反应没这么大，反正都是绕等长多绕圈，少绕几圈增加的工作量不算大，把Pin Delay的规则给我就行了……

本课程会通过一个正式仿真案例以确认在给定条件下在哪绕最好，同时给出不同的建议。

除了上面的一些典型常用问题名，本节课还会对《信号、电源完整性仿真设计与高速产品应用实例》书中时序的内容深入讲解。

主要大纲如下：

课程提纲

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